`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/31 11:53:11
// Design Name: 
// Module Name: inst_fetch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module inst_fetch(
    clk,reset_n,nop_b,nop_j,nop_fw,addr,addr_ir,inst,op_j_exe,op_b_mem,offset_j,offset_b_mem,addr_next,zero_mem,nop_j_out,nop_b_out,lu,
    addr_next_id,addr_next_exe
    );

    input clk,reset_n,nop_b,nop_j;
    input [31:0] addr,offset_j,offset_b_mem,addr_next_id,addr_next_exe;
    input op_j_exe,op_b_mem;
    input zero_mem;
    input lu,nop_fw;
    output [31:0] inst;
    output [31:0] addr_ir,addr_next;
    output nop_j_out,nop_b_out;

    wire nop;

    assign nop = nop_b || nop_fw || nop_j;

    register_pc register_pc(.clk(clk),.reset_n(reset_n),.addr(addr),.addr_ir(addr_ir),.op_j_exe(op_j_exe),.op_b_mem(op_b_mem),
    .offset_j(offset_j),.offset_b_mem(offset_b_mem),.addr_next(addr_next),.zero_mem(zero_mem),.nop_b_out(nop_b_out),
    .nop_j_out(nop_j_out),.lu(lu),.nop(nop),.addr_next_id(addr_next_id),.addr_next_exe(addr_next_exe));
    mem_inst mem_inst(.clk(clk),.reset_n(reset_n),.addr_ir(addr_ir),.inst(inst),.nop(nop));
endmodule
